We propose here an implementation of 2D hierarchical clustering tailored for power constrained and low-precision hardware. In many application fields such as smart sensor networks, having low computational capacity is mandatory for energy saving purposes. In this context, we aim to deploy a specific constrained hardware solution, using a parallel architecture with a low number of bits. The effectiveness of the proposed approach is corroborated by testing it on well-known 2D clustering datasets. Numerical results show how our low power solution can be implemented without affecting clustering accuracy.
An energy-aware hardware implementation of 2D hierarchical clustering / Cardarilli, G. C.; Fazzolari, R.; Matta, M.; Panella, M.; Rosato, A.; Spano, S.. - (2020), pp. 1-5. (Intervento presentato al convegno 2020 IEEE International Conference on Environment and Electrical Engineering and 2020 IEEE Industrial and Commercial Power Systems Europe, EEEIC / I and CPS Europe 2020 tenutosi a Madrid; Spain) [10.1109/EEEIC/ICPSEurope49358.2020.9160773].
An energy-aware hardware implementation of 2D hierarchical clustering
Panella M.
;Rosato A.;
2020
Abstract
We propose here an implementation of 2D hierarchical clustering tailored for power constrained and low-precision hardware. In many application fields such as smart sensor networks, having low computational capacity is mandatory for energy saving purposes. In this context, we aim to deploy a specific constrained hardware solution, using a parallel architecture with a low number of bits. The effectiveness of the proposed approach is corroborated by testing it on well-known 2D clustering datasets. Numerical results show how our low power solution can be implemented without affecting clustering accuracy.File | Dimensione | Formato | |
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